FIG. 1 shows the architecture of a typical sigma-delta DAC. For the sake of explanation, this example is labelled with data that would arise in an audio application although the architecture can be used in a wide range of applications. A digital data signal (e.g. 16 bit audio data at a rate of 48 kHz) is upsampled by an interpolator 2 at some multiple of the original data rate. In this example the upsampling ratio is (6.144 MHz/48 kHz)=128x. The resulting oversampled digital signal is applied to a multi-bit sigma-delta modulator 3. The multi-bit digital data output by the modulator 3 is applied to a multi-bit current DAC 4 to generate a multi-level analog current signal. This is converted to an analog voltage signal by a current-to-voltage converter 5. Finally, the stepped voltage signal is applied to a low pass filter 6 to provide a smoothed analog output signal.
FIGS. 2 and 3 show generalized topologies for the IDAC and I–V converter stages 4, 5 of the DAC of FIG. 1. For a multi-bit IDAC the IDAC comprises a set of unit current digital-to-analog converters (IDAC) 50, i.e. a set of IDACs which each have the same value current source. For clarity, only one such unit IDAC is shown in detail in FIG. 2. Two biasing current sources 31, 32 each supply a bias current to balance the current from the IDAC 55 in midscale condition. The unit IDACs 50 can each have their current selectively steered via switches 53, 54 to draw current out of node ‘Outb’ 41 or node ‘Out’ 42 in the circuit. The IDAC receives a multi-bit digital word which is used to vary the current that is produced but the IDAC 55. The switches 53, 54 can be switched in a symmetrical manner or, if rise and fall times are mismatched, a dual return-to-zero switching scheme can be used. FIG. 3 shows an arrangement for dual return-to-zero operation, with two biasing current sources 51, 52, a set of switches 53, 54, 56, 57 which are driven by a dual return-to-zero driver. The paper “A 113 dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling”, Adams. R et al presented at the 45th IEEE Solid-State Circuits Conference (ISSCC) 5–7 Feb. 1998 and published in the accompanying Digest of Technical Papers at p. 62–63, 413 describes a multi-bit CT sigma-delta DAC with a scrambler placed between the output of a sigma-delta modulator and the input to a current DAC.
The technology trend towards very deep sub-micron processes dictates lower power supply voltages. Continuous-time DACs are well suited to these processes. However, one limitation in achieving very high performance for continuous-time DACs in deep sub-micron technology is flicker noise. For the specialized case of using the DAC of FIG. 2 or 3 in a small sub-micron technology, the gate area of the MOS devices 51 used in the unit current sources within the IDAC 55 as well as the DC biasing current sources 31, 32 would require a excessive area in order to achieve low flicker noise. This is because flicker noise is inversely proportional to the area of a device. The input and output MOS devices of the amplifiers would also require a large gate area for achieving high performance. An alternative solution to reduce the area of the main flicker noise contributors would be desirable.
Accordingly, the present invention seeks to provide an improved sigma-delta DAC.